1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a program element such as a fuse.
2. Description of Related Art
FIG. 18 is a schematic circuit diagram of a conventional semiconductor integrated circuit device having a fuse element. In FIG. 18, reference numeral 101 designates a fuse element group (FUSEG); 102 designates a fuse state detection circuit group (FDG) for detecting the ON/OFF state of fuse elements; 103 designates a random access memory or RAM; 1031 designates a main memory access array (MMCA); 1032 designates a redundancy memory cell array for columns (RMCAC); and 1033 designates a redundancy memory cell array for rows (RMCAR). Reference symbols F0-F3 each denote a fuse element; and FD denotes a fuse state detection circuit.
Here, the fuse elements F0, F1, F2, and F3 in the fuse state detection circuit group 101 can be cut or shorted according to information to be programmed by current, laser beam, voltage, and so on. Though only the four fuses are depicted in FIG. 18, a real semiconductor integrated circuit device is constructed by containing more than four fuses.
On the other hand, each fuse state detection circuit FD in the fuse state detection circuit group 102 detects the ON/OFF state of whether the corresponding fuse is cut or not, and then outputs xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d as a logic signal. The fuse state detection circuit group 102 outputs the information of a plurality of bits.
As to the RAM 103, in FIG. 18, reference symbol A denotes an address terminal; WE denotes a write enable terminal; and DIO denotes a data input/output terminal, which may be replaced by a terminal provided with an data input terminal and a data output terminal discretely. In response to information output from the fuse state detection circuit group 102, the RAM 103 can replace part of the main memory cell array 1031 with the corresponding part of the redundancy memory cell array for columns 1032 or the redundancy memory cell array for rows 1033. Such a function is utilized for the correction or relief of a defective memory cell of the main memory cell array.
The redundancy memory cell array for columns 1032 is applied for the correction of a bit line fault and an in-cell fault, while the redundancy memory cell array for rows 1033 is applied for the correction of a word line fault and an in-cell fault.
Next, FIG. 19 is another schematic circuit diagram of a conventional semiconductor integrated circuit device having a fuse element. In FIG. 19, reference numeral 104 designates an (Error Checking and Correcting) error correction circuit which detects an error in a data transmission of ECC code and corrects the corresponding error point. The ECC is explained as follows: In order to detect an error and further correct this, bits for error detection or correction based on a certain rule are added to original data. Note that the same other numerals above denote the same or corresponding parts.
The semiconductor integrated circuit device as shown in FIG. 19, in addition to the circuit configuration of FIG. 18, is further added the ECC error correction circuit 104 to the fuse section, thus improving the yield of the semiconductor integrated circuit device. In this example, three bits for checking of F4, F5 and F6 is added to four information bits of F0, F1, F2 and F3. That error correction method is disclosed in JP-B-5/82000.
Further, FIG. 20 is yet another schematic circuit diagram of a conventional semiconductor integrated circuit device, which disposes a plurality of RAMs having a fuse element as shown in FIGS. 18 and 19. In FIG. 20, reference numerals 101-1 to 101-n (n: natural number) each designate a fuse element group; 102-1 to 102-n each designate a fuse state detection circuit group; 103-1 to 103-n each designate a RAM; and 105 designates a random logic circuit, which carries out a control and data input/output for the RAMs 103-1 to 103-n.
For this reason, the circuit configuration of FIG. 20 requires a plurality of circuit compositions corresponding to n out of the fuse element groups 101-1 to 101-n, fuse state detection circuit groups 102-1 to 102-n, RAMs 103-1 to 103-n, and ECC error correction circuits 104-1 to 104-n. Note that the ECC error correction circuits 104-1 to 104-n are eliminated if not required.
FIGS. 21A and 21B are examples of circuit diagrams illustrating CRC (Cyclic Redundancy Code) circuits which correspond to conventional error correction techniques. FIG. 21A illustrates a CRC generation circuit, and FIG. 21B illustrates a CRC correction circuit. In FIGS. 21A and 21B, reference symbols G1 to G3, D1 to D3, and S0 to S6 each denote a flip-flop (FF).
These examples correspond to the CRC circuits of a characteristic polynominal: G(x)=1+X+X3. The CRC generation circuit of FIG. 21A adds check bits of 3 bits to information bits of 4 bits, while the CRC correction circuit of FIG. 21B input a CRC of 7 bits and corrects an error of 1 bit and can correct the error of 1 bit at any position in the 7 bits. However, the error of 2 bits or more cannot be corrected.
Hereinafter, the operation of the aforementioned circuits will be described briefly.
(1) As to Generation Operation of CRC (Referring to FIG. 21A):
(1-1) Reset the flip-flops G1, G2, and G3 (reset means not depicted).
(1-2) In a state that the signal input of SELSIG terminal is SELSIG=1, a clock is provided for the flip-flops G1, G2, and G3 while the information bits of 4 bits to SIG terminal is inputted in series. At this time, the information bits of 4 bits is transferred at SEG terminal as it stands, and simultaneously the data of the check bits is generated in the flip-flops G1, G2, and G3.
(1-3) In a state that the signal input of SELSIG terminal is SELSIG=0, the data of the flip-flops G3, G2, and G1 are outputted to SOG terminal in series.
On the basis of the above operation, the CRC of 7 bits (4 bits+3 bits) is outputted from the SOG output terminal.
(2) As to Error Correction Operation of CRC (Referring to FIG. 21B):
(2-1) Reset the D1, D2, and D3 to xe2x80x9c0xe2x80x9d (reset means not depicted).
(2-2) clocks are supplied0 for the flip-flops D1 to D3 and S0 to S6 while the CRC of 7 bits are inputted in series from SIC terminal. Here, at the moment time the CRC of 7 bits is stored in the flip-flops S0 to S6, error detection results of the flip-flop S0 to the bits are outputted from COR output (xe2x80x9c1xe2x80x9d is outputted when an error exists). Accordingly, in SOC terminal, error corrected data is outputted to the bit of the flip-flop S0.
In FIGS. 9 and 11, the fuses F4 to F6 and flip-flops S4 to S6 are assigned to the check bits, while the fuses F0 to F3 and flip-flops S0 to S3 are assigned to the information bits. However, it is possible to change such an assignment. For example, the following is considered: the fuses F0 to F2 and flip-flops S0 to S2 are assigned to the check bits, while the fuses F3 to F6 and flip-flops S3 to S6 are assigned. In this case, the circuit must be changed to construct a counter with the flip-flops S3 to S6, but not depicted since it is inferred with ease.
(2-3) In a state that the signal input of SIC terminal is SIC=0, clocks are supplied for the flip-flops D1 to D3. Thus, an error detection result corresponding to the bit of the flip-flop S0 is outputted to the COR output (xe2x80x9c1xe2x80x9d is outputted when an error exists). Accordingly, in SOC terminal, error corrected data is outputted to the bit of the flip-flop S0.
(2-4) In a state that the signal input of SIC terminal is SIC=0, when clocks according to 6 cycles are supplied for the flip-flops D1 to D3 and S0 to S6, error corrected data is outputted in series from SOC terminal with respect to the remaining 6 bits.
However, when only the information bits of 4 bits are required, it is reasonable to perform the error correction operation for only the front 4 bits. Accordingly, the error correction operation of the subsequent check bits of 3 bits is not required.
As described above, in the digital communication, the error correction technique which enables an error correction of 1 bit has been gone into actual use by the CRC technique.
Since the conventional semiconductor integrated circuit device is constructed in the circuit as described above, as shown in FIG. 20, the corresponding plural sets of the fuse element groups 101-1 to 101-n, fuse state detection circuit groups 102-1 to 102-n, and ECC error correction circuits 104-1 to 104-n are required, resulting in an area increase of the semiconductor integrated circuit device and increasing the production cost.
The present invention is implemented to solve the foregoing drawbacks. It is therefor an object of the present invention to provide a semiconductor integrated circuit device which controls an area increase related to a program element, improving the production yield, and further reducing the production cost.
A semiconductor integrated circuit device according to the present invention is characterized in that when a parallel/serial conversion circuit converts the separation information of a program element group such as one fuse element group to serial data, the serial data is transmitted through a serial/parallel conversion circuit, thus controlling circuits to be controlled such as a plurality of RAMS. Further, it is characterized by introducing a CRC technique in the parallel/serial conversion circuit, even when there is an error input such as separation error of the fuse element, the information may be reproduced.
More specifically, according to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a plurality of circuits to be controlled; a plurality of program elements; a program state detection circuit group for converting program states of said program elements to a plurality of logic signals; a parallel/serial conversion circuit for converting the logic signals outputted from said program state detection circuit group to serial data; and one or a plurality of serial/parallel conversion circuits for receiving and supplying said serial data.
Here, said parallel/serial conversion circuit may include a CRC error correction circuit.
The parallel/serial conversion circuit may include a counter circuit capable of setting part of all of parallel input data as a primary value; and a specific state detection circuit for detecting a specific state of said counter circuit, thereby transmitting the output of said specific state detection circuit to said serial/parallel conversion circuit as serial data.
The program element may be a fuse element to be fused.
One of said circuits to be controlled may be a memory circuit having a redundancy memory cell array, a power supply circuit, or a timing generation circuit.